In the manufacturing process for a semiconductor device or the like, when testing the electrical characteristics of a target test object (to be referred to as “device” hereinafter) formed on a wafer-like substrate (to be merely referred to as “wafer” hereinafter) W, a prober shown in, e.g., FIGS. 4A and 4B, is used. The prober has a loader chamber 1 and prober chamber 2. A test head T for a tester 27 is pivotally arranged on a head plate 9 arranged on the prober chamber 2. The test head T is electrically connected to a probe card 7 and a plurality of probes 7A provided to the probe card through a performance board (not shown). A test signal transmitted from the tester 27 is sent to the probes 7A through the test head T and the performance board. The probes 7A apply test signals to the electrode pads of a device formed on the wafer W. Thus, the electrical characteristics of the device, e.g., a plurality of semiconductor devices (chips), formed on the wafer W are tested.
The test signals are transmitted from the tester 27 to the probes 7A through signal lines. If all the signal lines and the probes 7A have the same physical characteristics, the test signals can be correctly transmitted to the plurality of probes 7A through the performance board. Therefore, the probes 7A can apply the test signals to the electrode pads with the same phase, so that the device can be tested correctly. Due to a slight difference in the manufacturing process, however, sometimes the physical characteristics of the respective signal lines and the respective probes 7A differ slightly from each other. As the test signals are very sensitive, a slight difference in physical characteristics of the probes 7A may sometimes cause, e.g., a phase difference, among the test signals that have arrived the distal ends of the probes 7A. If the test signals have a phase difference or the like, it is difficult to correctly test the device.
As a technique for calibrating the phase difference of the signals, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-352578 discloses a technique related to a timing calibration method for an IC test device. According to the timing calibration method described in Jpn. Pat. Appln. KOKAI Publication No. 2000-352578, delay time difference among signals from times at the signal generation to times at the signal arrival due to difference in the length of signal transmission lines of the IC test device can be calibrated. Due to the manufacturing process or the like, however, if the physical characteristics of the signal lines or the like differ slightly, and accordingly the timings at which signals of the respective signal lines arrive differ, this difference in timing cannot be calibrated. This timing calibration method is concerned with an IC test device. In the prober, the arrival times of signals, which transmitted from the tester to the probe card, differ depending on the physical characteristics of the respective signal lines. It is recognized that, in order to calibrate the arrival times of the respective signals, the signals must be detected at the distal ends of the respective probes. It is, however, difficult to detect the signals at the distal ends of the probes, and accordingly it is difficult to detect and calibrate the difference among the plurality of test signals.